EDN

How to improve FPGA-based ASIC prototyping with SystemVerilog

ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs. However, creating an ASIC is a high-investment ...
Design-Reuse

Silicon Interfaces announces the release of its Open Verification Methodology (OVM) Based Gigabit Ethernet MAC SystemVerilog OVC

CAMPBELL, Calif., October 16, 2008-- Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, announces the availability of their Gigabit ...
EDN

SystemVerilog goes to next level

IEEE Standard 1800-2005 SystemVerilog is the industry's first unified hardware description and verification language. A major extension of the established IEEE Std 1364-2001 Verilog language, it ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.